This invention relates to a memory for a glass container inspection machine. More particularly, this invention relates to a memory for a glass container inspection machine which indexes glass containers from station to station for inspection. Specifically, this invention relates to a solid state memory for such an inspection machine.
One well-known type of inspection machine for glass containers is that known as the FP machine, manufactured by Owens-Illinois, Inc. This is a rotary, indexing machine where glass containers are indexed through a plurality of stations for inspection. A defect may be found at any station, but rejection of a defective container cannot occur until the last inspection station has been passed. Thus, these machines require a memory to allow retention of defective container information until a rejection location is reached. In the past, pin-type or magnetic belt memories have been used. However, these are basically mechanical devices which have presented not only maintenance problems but also accuracy of information storage problems. I have devised a solid state memory for this machine which uses reliable, durable electronic components. This reduces maintenance problems and raises the reliability with which the memory is retained. A very fast clock pulse is used to clock a group of series-connected flip-flops in a time less than the transfer time of information through the flip-flops.
Memory systems of this general type are not unknown in the prior art. For example, see U.S. Pat. Nos. 3,259,240; 3,263,810; 3,565,249; and 3,581,889. The best example of the prior art known to me is U.S. Pat. No. 3,757,940. This patent teaches a solid state memory for a similar FP type machine. The memory of the cited patent has been successful, but it is quite complex and is designed for very high speed operation. It requires two memories and two separate clock frequencies to allow downstream rejection of the defective containers. In addition, the clock pulses must be delayed and conditioned to avoid false shifts of information. My invention is designed for FP machines which operate at moderate speeds and do not require downstream rejection. In addition, I have simplified the circuit of the cited patent and eliminated the need for delay and conditioning of the clock pulses. Furthermore, my clock pulse generation technique is much simpler since only a single clock pulse at a single frequency is required.